Silicon Photonics Workshop

As data demands surge, 400G per lane is emerging as the next-generation interconnect technology. This talk reviews the silicon photonics components critical to enabling 400G performance, including modulators and detectors. We will highlight recent advances, key challenges, and the role of integration in paving the way for scalable, energy-efficient optical interconnects.

Po Dong Bio

Vice President of Silicon Photonics Technology at Coherent, where he leads the company’s silicon photonics product developments. Prior to joining Coherent, he served as a Department Head at Nokia Bell Labs. In recognition of his impactful contributions to the field, Po Dong has been elected a Fellow of both IEEE and Optica (formerly OSA).

This presentation explores the transformative role of co-packaged optics with integrated silicon photonics in accelerating large-scale AI development. These technological innovations significantly enhance energy efficiency and scalability for AI applications by reducing electrical loss, improving resilience, and optimizing network performance within data center architectures. Strong industry collaboration and ecosystem partnerships are essential to continue advancing these technologies, enabling high-density, high-bandwidth connectivity for robust AI networking.

Janet Chen Bio

Janet is the Director of Silicon Photonics Development at NVIDIA, leading product development and strategic initiatives in optical interconnect technologies. Her career spans both research and industry, with technical and business leadership roles at NTT Photonics Labs, HP Labs, FOIT, Neophotonics, Meta, and Lumentum. She received her PhD from the University of California, Santa Barbara and is also a Senior Member of IEEE.

This presentation delves into the cutting-edge advancements in silicon photonics, which are pivotal for addressing the escalating requirements for high-speed, energy-efficient interconnects. We will discuss the state-of-the-art technologies based on SOI and SiN platforms, along with heterogeneous and 3D integration strategies that tackle the challenges presented by generative AI and high-performance computing applications. The talk will elucidate how these innovations are revolutionizing optical interconnects and laying the groundwork for future developments in high-bandwidth, low-latency communication systems. Attendees will gain insights into the latest research and development efforts aimed at CEA-Leti for enhancing computational performance and reducing energy consumption in next-generation interconnect solutions.

Éléonore Hardy Bio

She joined CEA-Leti in 2018 as a business developer specializing in silicon photonics. She holds a Master’s degree in Engineering and has completed a Master of Science in Management & Innovation. With over 20 years of experience in the optics and photonics industry, Éléonore has held key positions at Philips in the Netherlands and Varioptic, a business unit of Corning, in China.

Throughout her career, Éléonore has demonstrated a proven track record of creating long-term value. She successfully developed laser technologies in France, China, and India for Quantel (now Lumibird) and advanced spectrometer solutions in Europe and Asia for Resolution Spectra Systems (now part of Merck). Currently, Éléonore is focused on identifying and developing new business opportunities in silicon photonics, with a particular emphasis on high-speed optical interconnects, high-performance computing (HPC), 3D sensing, and advanced computing technologies such as neuromorphic computing and quantum photonics.

As Silicon Photonics is growing to a mainstay, key-enabling technology for general-purpose datacenters and AI factories networking, hyperscalers and application providers keep asking for more. In this talk, we will provide a brief, comprehensive overview of ST vision and ambitions for Silicon Photonics optical transceivers and co-packaged optics (CPO) technologies, aiming at strengthening the industrial maturity and performance of 100Gbaud/lane SiPho solutions – notably leveraging 300-mm process, high yields, and advanced packaging – as well as providing the market with continuous innovations, including TSV enablement and roadmaps to welcome future optical techs such as integrating heterogeneous materials for 200+Gbaud/lane transceiver implementations.

AI and data center workloads demand disruptive advances in photonics integration. This presentation will show how Soitec’s engineered substrates - SOI, InPoSI and LNOI/TFLN address today key challenges in Co-Packaged optics (CPO) and 400G per lane pluggables. We will highlight our innovations enabling higher performance, lower power and scalable manufacturing paving the way for next generation of photonics devices powering the AI revolution